An etch back process for fabricating a frame for an integrated circuit package is disclosed in U.S. Pat. No. 6,498,099, assigned to the assignee of the present application, the entire contents of which are incorporated herein by reference. According to this process, a copper substrate strip is first subjected to a partial etch on one or both of the top and bottom surfaces to create a pattern of contact leads (pads) and a die attach pad (paddle). After wire bonding the contacts to a singulated semiconductor die, followed by overmolding and curing of the mold, the leadframe strip is exposed to a second immersion etch for exposing the contact pads in an array pattern (i.e. multi-row) or perimeter pattern (i.e. single row), as well as the die attach pad. In the case of a package with multi-row I/O leads, this etch back step eliminates the previously required two additional saw singulation operations (i.e. to sever the inner leads from the outer leads), and in both the single-row and multi-row configurations, the etch back step eliminates the previously required post mold processing steps (e.g. mold deflashing) and ensures superior device yield over prior processing techniques. Additionally, this technique allows for higher I/O pad density and pad standoff from the package bottom compared to prior art techniques, thereby reducing stress in the solder joint during PCB temp cycling. Further, the technique allows for the use of a pre-singulation strip testing technique since the electrical I/O pads are isolated from each other. This feature greatly increases the handling and throughput of the test operation as compared to prior processes.
According to co-pending U.S. patent application Ser. No. 09/802,678 for a Leadless Plastic Chip Carrier With Etch Back Pad Singulation, assigned to the assignee of the present application, the entire contents of which are incorporated herein by reference, a build up fabrication process is provided. The build up process is carried out on a copper substrate strip. Metal layers are selectively plated up on the copper substrate strip to provide built-up die attach pads, each circumscribed by at least one row of contact pads (I/O pads) on the copper strip. After the build up process, semiconductor dice are fixed to respective die attach pads and gold wires are bonded between pads of the semiconductor dice and respective contact pads. The packages are then molded by placing the substrate strip in a mold. Following molding of the packages, the copper substrate strip is etched away to expose the die attach pad and the contact pads of each package.
Flip chip packages have become possible with advances in package fabrication including forming and placing of solder balls. Such packages are desirable due to increased electrical and mechanical performance. Direct connection of the semiconductor die to a pad frame surface in a flip-chip orientation, using solder ball connections provides low impedance packages relative to the use of wire-bond connections and provides reduced package space. Popularity of flip chip, thin array plastic packages has been limited by fabrication and cost of manufacture of pad frames, however.
Further developments in packaging technology are therefore driven by demand for improved reliability, electrical performance, decreased size and cost of manufacture.